1. Field of the Invention
The present invention relates to a semiconductor device test system, and more particularly, to a system for effectively testing a semiconductor device having many pins using test equipment having few pins.
2. Description of the Related Art
In general, testing a semiconductor device involves a process in which the DC characteristics, AC characteristics, and functions of a semiconductor device are tested using a test system. Testing the functions of a semiconductor device is generally performed by using the test system to generate predetermined input signal patterns. The input signal patterns are applied to input pins of the device. The test system then receives and compares output signal patterns from the device to predicted output signal patterns. In order to test the functions of the semiconductor device, the test system must be electrically connected to all of the pins of a device under test (DUT). To make this connection, a test head of the test system generally includes a pin electronics (PE) card that is used to electrically connect the test system to each of the pins of the DUT.
Conventionally, the PE card includes a number of channels at least equal to the number of pins in the DUT. That is, in the conventional semiconductor test system, if the number of pins in the DUT is N, the number of channels in the PE card of the test system must be also be N or more. The PE card channels are connected to the pins of the DUT. As a result, when a device has more pins than channels in the semiconductor test system, upgrades to the test system, such as expanding the PE card and increasing pattern memory, are required. When upgrades to the semiconductor test system are no longer feasible, such as when the PE card cannot be expanded any further, the conventional test system can no longer effectively test the characteristics of the semiconductor device.
FIG. 1 illustrates a conventional semiconductor device test system. Referring to FIG. 1, the conventional test system includes a test head 10 having at least one PE card 12. The PE card 12 includes a plurality of comparator and driver units 120_1, . . . , 120—i. Each comparator and driver unit 120_1, . . . , 120—i includes one comparator CP and one driver DR. Pattern data stored in a pattern memory (not shown) is applied to the pins of a DUT 20 by the driver DR, and data output from the pins of the DUT 20 is compared with predicted data. If the output data is the same as the predicted data, the DUT 20 is functioning normally. If the output data is not the same as the predicted data, the DUT 20 is not functioning normally.
The conventional test system's ability to test a semiconductor device having many pins is limited because each comparator and driver unit 120_1, . . . , 120—i corresponds to a single pin of the DUT 20. A semiconductor device having more pins than the test system cannot be tested using a conventional semiconductor test system and method, and upgrading the conventional semiconductor test system for testing a semiconductor device increases test cost.